Content addressable memory (CAM) devices are frequently used in network switching and routing applications to determine forwarding destinations, to perform classification functions, to implement Quality of Service (QoS) functions, and to perform other tasks associated with routing data packets across a network. More specifically, a CAM device includes a CAM array having a plurality of CAM cells organized in a number of rows and columns. Each row of CAM cells, which can be used to store a CAM word, is coupled to a corresponding match line that indicates match results for the row. During a compare operation, a search key is provided to the CAM array and compared with the CAM words stored therein. For each CAM word that matches the search key, a corresponding match line is asserted to indicate the match condition, and a priority encoder determines the match address or index of the highest priority matching (HPM) entry in the CAM array.
More specifically, the match lines of the CAM array are typically pre-charged to a logic high state (e.g., towards VDD) prior to the compare operation. During the compare operation, if all CAM cells in a row match the comparand data, the CAM cells do not discharge the row's match line, which remains in its charged state to indicate a match condition for the row. Conversely, if any CAM cell in the row does not match the comparand data, the CAM cell discharges the match line to a logic low state (e.g., towards ground potential) to indicate a mismatch condition for the row. The discharged match lines are pre-charged for the next compare operation.
Thus, for each row having a mismatch condition, an associated match line is first charged high towards VDD and then discharged low towards low ground potential. Current flow associated with charging and discharging match lines during successive compare operations results in undesirable power consumption. Accordingly, there is a need to minimize the power consumption associated with performing compare operations in CAM arrays.